(Hong Kong)
Product Summary
The K4H561638H-ZCB3 is a 268,435,456 bits of double data rate synchronous DRAM organized as 4x 4,194,304 words by 16bits, fabricated with high performance CMOS technology. The K4H561638H-ZCB3 features with Data Strobe allow extremely high performance up to 333Mb/s per pin. I/O transactions of the K4H561638H-ZCB3 are possible on both edges of DQS. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.
Parametrics
K4H561638H-ZCB3 absolute maximum ratings: (1)Voltage on any pin relative to VSS, VIN, VOUT: -0.5 to 3.6 V; (2)Voltage on VDD & VDDQ supply relative to VSS, VDD, VDDQ: -1.0 to 3.6V; (3)Storage temperature, TSTG: -55 to +150℃; (4)Power dissipation, PD :1.5 W; (5)Short circuit current, I: 50 mA.
Features
K4H561638H-ZCB3 features: (1)VDD: 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333; (2)VDD: 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400; (3)Double-data-rate architecture; two data transfers per clock cycle; (4)Bidirectional data strobe [L(U)DQS] (x16); (5)Four banks operation; (6)Differential clock inputs(CK and CK); (7)DLL aligns DQ and DQS transition with CK transition; (8)MRS cycle with address key programs; (9)All inputs except data & DM are sampled at the positive going edge of the system clock(CK); (10)Data I/O transactions on both edges of data strobe ; (11)Edge aligned data output, center aligned data input; (12)LDM,UDM for write masking only (x16); (13)Auto & Self refresh; (14)7.8us refresh interval(8K/64ms refresh); (15)Support Industrial Temp (-40 to 85℃); (16)Maximum burst refresh cycle : 8; (17)66pin TSOP II, 60Ball FBGA Pb-Free(RoHS compliant) package.
Diagrams
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 K4H510438B-G(Z)C/LA2 |
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K4H510438B-G(Z)C/LB0 |
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K4H510438B-G(Z)C/LB3 |
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K4H510438B-G(Z)C/LCC |
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K4H510438C-UCA2 |
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Negotiable |
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K4H510638E-LA2 |
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Negotiable |
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