(Hong Kong)
Product Summary
The MT48LC64M8A2P-75 is a 512Mb SDRAM. The MT48LC64M8A2P-75 is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 134,217,728-bit banks is organized as 8,192 rows by 4,096 columns by 4 bits. Each of the x8’s 134,217,728-bit banks is organized as 8,192 rows by 2,048 columns by 8 bits. Each of the x16’s 134,217,728-bit banks is organized as 8,192 rows by 1,024 columns by 16 bits.
Parametrics
MT48LC64M8A2P-75 absolute maximum ratings: (1)Voltage on VDD, VDDQ Supply Relative to VSS: -1V to +4.6V; (2)Voltage on Inputs, NC or I/O Pins Relative to VSS: -1V to +4.6V; (3)Operating Temperature, TA (Commercial): 0℃ to +70℃; (4)Storage Temperature (plastic): -55℃ to +150℃; (5)Power Dissipation: 1W.
Features
MT48LC64M8A2P-75 features: (1)PC100- and PC133-compliant; (2)Fully synchronous; all signals registered on positive edge of system clock; (3)Internal pipelined operation; column address can be changed every clock cycle; (4)Internal banks for hiding row access/precharge; (5)Programmable burst lengths: 1, 2, 4, 8, or full page; (6)Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes; (7)Self Refresh Mode; (8)64ms, 8,192-cycle refresh; (9)LVTTL-compatible inputs and outputs; (10)Single +3.3V ±0.3V power supply.
Diagrams
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 MT48LC64M8A2P-75 IT:C |
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IC SDRAM 512MBIT 133MHZ 54TSOP |
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MT48LC64M8A2P-75 IT:C TR |
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IC SDRAM 512MBIT 133MHZ 54TSOP |
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MT48LC64M8A2P-75 L:C |
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IC SDRAM 512MBIT 133MHZ 54TSOP |
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Negotiable |
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MT48LC64M8A2P-75:C TR |
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IC SDRAM 512MBIT 133MHZ 54TSOP |
Data Sheet |
Negotiable |
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MT48LC64M8A2P-75:C |
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IC SDRAM 512MBIT 133MHZ 54TSOP |
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