MT46V32M16BN-6 IT:F

Product Summary

The MT46V32M16BN-6 IT:F is a 512Mb DDR SDRAM. The MT46V32M16BN-6 IT:F is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM. The MT46V32M16BN-6 IT:F uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 512Mb DDR SDRAM effectively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

Parametrics

MT46V32M16BN-6 IT:F absolute maximum ratings: (1)VDD Supply Voltage Relative to VSS: -1V to +3.6V; (2)VDDQ Supply Voltage Relative to VSS: -1V to +3.6V; (3)VREF and Inputs Voltage Relative to VSS: -1V to +3.6V; (4)I/O Pins Voltage Relative to VSS: -0.5V to VDDQ +0.5V; (5)Operating Temperature, TA (ambient): 0℃ to +70℃; (6)Storage Temperature (plastic): -55℃ to +150℃; (7)Power Dissipation: 1W; (8)Short Circuit Output Current: 50mA.

Features

MT46V32M16BN-6 IT:F features: (1)VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V; (2)Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture (x16 has two – one per byte); (3)Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle; (4)Differential clock inputs (CK and CK#); (5)Commands entered on each positive CK edge; (6)DQS edge-aligned with data for READs; center-aligned with data for WRITEsDLL to align DQ and DQS transitions with CK; (7)Four internal banks for concurrent operation; (8)Data mask (DM) for masking write data (x16 has two-one per byte); (9)Programmable burst lengths: 2, 4, or 8; (10)x16 has programmable IOL/IOV.; (11)Concurrent auto precharge option is supported; (12)Auto Refresh and Self Refresh Modes; (13)Longer lead TSOP for improved reliability (OCPL); (14)2.5V I/O (SSTL_2 compatible).

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