ORT8850L-2BM680C-1I

Product Summary

The ORT8850L-2BM680C-1I is a Field Programmable System-on-a-Chip (FPSC). It brings a whole new dimension to programmable logic: Field Programmable Gate Array (FPGA) logic and an embedded system solution on a single device. Lattice has developed a solution for designers who need the many advantages of FPGA-based design implementation, coupled with high- speed serial backplane data transfer. Built on the Series 4 recond-gurable embedded System-on-a-Chip (SoC) architecture, the ORT8850L-2BM680C-1I is made up of backplane transceivers (SERDES) containing eight channels, each operating at up to 850 Mbits/s (6.8 Gbits/s when all eight channels are used).

Parametrics

ORT8850L-2BM680C-1I absolute maximum ratings: (1)Storage Temperature Tstg: -65 to 150℃; (2)Power Supply Voltage with Respect to Ground VDD332: -0.3 to 4.2 V; VDDIO: -0.3 to 4.2 V; VDD15: -0.3 to 2.0 V; VDDA_STM1: -0.3 to 2.0 V; (3)Input Signal with Respect to Ground: -0.3 to VDDIO + 0.3 V; (4)Signal Applied to High-impedance Output: -0.3 to VDDIO + 0.3 V; (5)Maximum Package Body (Soldering) Temperature: 220℃.

Features

ORT8850L-2BM680C-1I features: (1)Allows a wide range of high-speed backplane applications, including SONET transport and termination; (2)No knowledge of SONET/SDH needed in generic applications. Simply supply data, 78 MHz-106 MHz clock, and a frame pulse; (3)High-Speed Interface (HSI) function for clock/data recovery serial backplane data transfer without external clocks; (4)Eight-channel HSI function provides 850 Mbits/s serial interface per channel for a total chip bandwidth of 6.8 Gbits/s (full duplex); (5)HSI function uses Lattice’s 850 Mbits/s serial interface core. Rates from 126 Mbits/s to 850 Mbits/s are supported.; (6)LVDS I/Os compliant with EIA-644 support hot insertion. All embedded LVDS I/Os include both input and output on-board termination to allow long-haul driving of backplanes; (7)Low-power 1.5 V HSI core; (8)Low-power LVDS buffers; (9)Programmable STS-3, and STS-12 framing; (10)Independent STS-3, and STS-12 data streams per quad channels; (11)8:1 data multiplexing/demultiplexing for 106.25 MHz byte-wide data processing in FPGA logic.

Diagrams