(Hong Kong)
Product Summary
The R5S7266ZD144FP is a single-chip RISC (Reduced Instruction Set Computer) microprocessor that integrates a Renesas Technology original RISC CPU core with peripheral functions required for system configuration. The R5S7266ZD144FP incorporated in this LSI is the SH-2A CPU, which features upward compatibility on the object code level with the SH-1, SH-2, and SH-2E microcomputers. The R5S7266ZD144FP has a RISC-type instruction set and employs a superscalar architecture and the Harvard architecture, which greatly improves instruction execution speed.
Parametrics
R5S7266ZD144FP absolute maximum ratings: (1)Analog input capacitance : 20 pF; (2)Allowable signal-source impedance: 5 kΩ; (3)Power supply voltage (I/O)PVCC: -0.3 to 4.6 V; (4)Power supply voltage (Internal)VCCR: -0.3 to 4.6 V; (5)Power supply voltage (PLL)PLLVCC: -0.3 to 4.6 V; (6)Analog power supply voltage AVCC: -0.3 to 4.6 V; (7)Analog reference voltage AVref: -0.3 to AVCC +0.3 V; (8)Input voltage Analog input pin VAN: -0.3 to AVCC +0.3 V; (9)PC22 to PC25, PD15, PD16 Vin: -0.3 to 5.5 V; (10)Other pins Vin: -0.3 to PVCC +0.3 V; (11)Operating temperature Topr: -20 to +70°C (Regular specifications), -40 to +85°C (Wide-range specifications); (12)Storage temperature Tstg: -55 to +125 °C.
Features
R5S7266ZD144FP features: (1)Renesas Technology original SuperH architecture; (2)Compatible with SH-1 and SH-2 at object code level; (3)32-bit internal data bus; (4)Support of an abundant register-set; (5)RISC-type instruction set (upward compatible with SH series); (6)Superscalar architecture to execute two instructions at one time including FPU; (7)Instruction execution time: Up to two instructions/cycle; (8)Address space: 4 Gbytes; (9)Internal multiplier; (10)Five-stage pipeline; (11)Harvard architecture.
Diagrams
