XCV100-4PQ240C

XCV100-4PQ240C, Field Programmable Gate Array, 3.0 V, 50 ms, QFP

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Price:: US $56.00~56.00 / piece [Get Latest Price]

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PartNumber:: XCV100-4PQ240C

Brand:: Xilinx, Inc - Xilinx | Pack: QFP | D/C: 00+

Availability:: Supply Ability: 0/Day Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2013-05-24

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Part Number:XCV100-4PQ240C
US $56.00 - 56.00
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Product Summary

The XCV100-4PQ240C is a Field Programmable Gate Array. It delivers high-performance, high-capacity programmable logic solutions. Dramatic increases in silicon efficiency result from optimizing the new architecture for place-and-route efficiency and exploiting an aggressive 5-layer-metal 0.22 mm CMOS process. These advances make the XCV100-4PQ240C powerful and flexible alternatives to mask-programmed gate arrays. The XCV100-4PQ240C delivers a high-speed and high-capacity programmable logic solution that enhances design flexibility while reducing time-to-market.

Parametrics

XCV100-4PQ240C absolute maximum ratings: (1)VCCINT, Supply voltage relative to GND: –0.5 to 3.0 V; (2)VCCO, Supply voltage relative to GND: –0.5 to 4.0 V; (3)VREF, Input Reference Voltage: –0.5 to 3.6 V; (4)VIN, Input voltage relative to GND: Using VREF: –0.5 to 3.6 V; Internal threshold: –0.5 to 5.5 V; (5)VTS, Voltage applied to 3-state output: –0.5 to 5.5 V; (6)VCC, Longest Supply Voltage Rise Time from 1V-2.375V: 50 ms; (7)TSTG, Storage temperature (ambient): –65 to +150 ℃ ; (8)TJ, Junction temperature: Plastic Packages: +125 ℃.

Features

XCV100-4PQ240C features: (1)Fast, high-density Field-Programmable Gate Arrays: Densities from 50k to 1M system gates; system performance up to 200 MHz; 66-MHz PCI Compliant; Hot-swappable for Compact PCI; (2)Multi-standard SelectIO interfaces: 16 high-performance interface standards; Connects directly to ZBTRAM devices; (3)Built-in clock-management circuitry: Four dedicated delay-locked loops (DLLs) for advanced clock control; Four primary low-skew global clock distribution nets, plus 24 secondary local clock nets; (4)Hierarchical memory system: LUTs configurable as 16-bit RAM, 32-bit RAM, 16-bit dual-ported RAM, or 16-bit Shift Register; Configurable synchronous dual-ported 4k-bit RAMs; fast interfaces to external high-performance RAMs.