MPC866PCZP100A

MPC866PCZP100A, versatile single-chip integrated microprocessor, BGA, -0.3 to 4.0 V, Freescale Semiconductor

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Price:: US $41.00~41.00 / piece [Get Latest Price]

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Qty (lots)	Price/lot
1 ~ 100 :	41.00 / Piece

PartNumber:: MPC866PCZP100A

Brand:: Freescale Semiconductor, Inc - Freescale | Pack: BGA | D/C: 10+

Availability:: Supply Ability: 1000/Month Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

Quantity:: piece

Total Price:: US $0

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Products Upload time: 2013-05-10

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Part Number:MPC866PCZP100A
US $41.00 - 41.00
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Product Summary

The MPC866PCZP100A is a versatile single-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications and communications and networking systems. The MPC866PCZP100A provides enhanced ATM functionality over that of other ATM-enabled members of the MPC860 family.

Parametrics

MPC866PCZP100A absolute maximum ratings: (1)Supply voltage, VDDH: -0.3 to 4.0 V; VDDL: -0.3 to 2.0 V; VDDSYN: -0.3 to 2.0 V; (2)Difference between, VDDL to VDDSYN: 100 mV; (3)Input voltage, Vin, GND: -0.3 to VDDH V; (4)Storage temperature range, Tstg: -55 to +150℃.

Features

MPC866PCZP100A features: (1)The core performs branch prediction with conditional prefetch, without conditional execution; (2)4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache; (3)16-Kbyte instruction cache (MPC866P and MPC859P) is four-way, set-associative with 256 sets; 4-Kbyte instruction cache (MPC866T, MPC859T, and MPC859DSL) is two-way, set-associative; (4)with 128 sets; (5)8-Kbyte data cache (MPC866P and MPC859P) is two-way, set-associative with 256 sets; 4-Kbyte data cache(MPC866T, MPC859T, and MPC859DSL) is two-way, set-associative with 128 sets; (6)Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks; (7)Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis; (8)MMUs with 32-entry TLB, fully associative instruction and data TLBs; (9)MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces and 16 protection groups; (10)Advanced on-chip-emulation debug mode.