Product Summary

TheSY100S351FC is a six D-type, edge-triggered, master/slave flip-flop with differential outputs, and is designed for use in high-performance ECL systems. The SY100S351FC is controlled by the signal from the logical OR operation on a pair of common clock signals (CPa, CPb). Data enters the master when both CPa and CPb are LOW and transfers to the slave when either CPa or CPb (or both) go to a logic HIGH. The Master Reset (MR) input overrides all other inputs and takes the Q outputs to a logic LOW. The inputs on this device have 75KΩ pull-down resistors.

Parametrics

SY100S351FC absolute maximum ratings: (1)IEE Power Supply Current: –98 to –49 mA; (2)fMAX Toggle Frequency: 700 MHz; (3)VEE: –4.2V to –5.5V.

Features

SY100S351FC features: (1)Max. toggle frequency of 700MHz; (2)Clock to Q max. of 1200ps; (3)IEE min. of –98mA; (4)Industry standard 100K ECL levels; (5)Extended supply voltage option: VEE = –4.2V to –5.5V; (6)Voltage and temperature compensation for improved noise immunity; (7)Internal 75KΩ input pull-down resistors; (8)50% faster than Fairchild 300K; (9)Better than 20% lower power than Fairchild; (10)Function and pinout compatible with Fairchild F100K; (11)Available in 24-pin CERPACK and 28-pin PLCC packages.

Diagrams

SY100S351FC pin connection

Image Part No Mfg Description Data Sheet Download Pricing
(USD)
Quantity
SY100S351FC
SY100S351FC


IC FLIP FLOP HEX D 24-CERPACK

Data Sheet

Negotiable 
Image Part No Mfg Description Data Sheet Download Pricing
(USD)
Quantity
SY10/100E111
SY10/100E111

Other


Data Sheet

Negotiable 
SY10/100E111A/L
SY10/100E111A/L

Other


Data Sheet

Negotiable 
SY10/100E111AE/LE
SY10/100E111AE/LE

Other


Data Sheet

Negotiable 
SY10/100E154
SY10/100E154

Other


Data Sheet

Negotiable 
SY10/100E156
SY10/100E156

Other


Data Sheet

Negotiable 
SY10/100E157
SY10/100E157

Other


Data Sheet

Negotiable